As is well known, digital signals can be very accurate and very precise. Moreover, they have a wide variety of potential applications. It happens, however, that many phenomena (natural and unnatural) and signals of these phenomena are initially generated in an analog format. Nevertheless, with some notable exceptions, such as certain aircraft flight instruments (e.g. a vertical speed indicator), it is often more desirable to present these signals in a digital format. If so, there are many well-known electronic analog-to-digital (A/D) converter circuits that are available for this purpose.
Although A/D converters are widely used in many applications, they are still susceptible to several notable shortcomings, e.g. limited sampling rate, signal to quantization noise ratio (resolution), and spurious free dynamic range. It is difficult to increase the sampling rate beyond the state of the art due to the limited switching rate of individual transistors and circuits. Typical attempts at increasing A/D sample rate further have employed multiplexed architectures. However, these architectures suffer from poor spurious free dynamic range due to mismatch and timing error. Thus, increased sampling rate is achieved at the expense of dynamic range.
The architecture described herein uses a plurality of 1-bit A/D converters, arranged in a recurrent neural network architecture to provide a significantly increased network-sampling rate as compared to the individual converters. Each 1-bit A/D converter integrates the voltage on its input until a threshold is reached and then outputs a voltage pulse or spike. Feedback signals coordinate the charge-fire cycles of each A/D circuit so that the overall noise in the signal baseband of the power spectrum of output spikes is suppressed. This noise shaping results in a significantly improved signal to quantization noise ratio (SQNR) as compared to oversampling alone. Mismatch, which usually plagues other ADC architectures, is not an issue since each ADC is limited to 1-bit. Accordingly, by using this method, system performance can be increased without the disadvantages of multiplexed architectures. The resulting parallel rate coded spike train is sampled by 1-bit latches and counted by a series of digital adders. The final output is a 9-bit (8-bit with sign) digital signal at a 10 GHz sample rate.
By definition, a recurrent network is one in which the network's hidden unit activations or output values are fed back into the network as inputs. In this context, it can be shown that when an output value from a first A/D converter is fed back as input to a second A/D converter in the same network, the time sequence for the charge fire cycle of the second A/D converter is altered. Through the mechanisms of a recurrent network, a plurality of A/D converters can receive a same analog signal and self-organize so their respective outputs will queue, rather than interfere (overlap) with each other.
As mentioned above, the rate at which spike outputs appear in the output of an individual A/D converter circuit is proportional to the voltage magnitude of its analog input signal. Thus, by counting the number of spike outputs for a single A/D converter, during a predetermined time interval, a spike rate can be determined that is proportional to the magnitude of an analog signal input. To get this rate may, however, be difficult, if not impossible. This is particularly so, when very high spike rates are required from a single A/D converter (i.e. rates that are caused by high voltage input from an analog signal). In this case, in order to get an accurate rate, an extended period of time for sampling the spike outputs may be required. On the other hand, consider a relatively large number of A/D converters (e.g. 2,000) that are connected in parallel (i.e. they each receive a same analog signal). They will all exhibit the same spike output rate. The difficulty here is keeping the spike outputs sufficiently separated so they can be counted within a shorter period of time.
With the above in mind, consider the incorporation of a large number of A/D converter circuits in a recurrent network. In this case, the charge fire cycles of these A/D converters will self-organize to avoid overlapping each other. Also, as indicated above, it will still happen that the single analog signal will cause each individual A/D converter to have a same output spike rate. It then follows that if all the respective spike outputs of the A/D converter circuits can be sampled over a same, shorter time interval, the collective count can be used to obtain the actual spike rate. The consequence here is that relatively long time intervals for sampling (i.e. counting) are not required. Instead, even though some A/D converters may not generate an output in the time interval, collectively, the output count will still indicate a spike output rate that is representative of the analog input. Importantly, this can be repetitively done in much shorter time intervals than would otherwise be required.
In light of the above, it is an object of the present invention to provide a system for converting an analog signal into a digital data stream which incorporates a recurrent network that will queue the respective spike outputs from, a plurality of A/D converters to create a parallel rate coded spike train that is characteristic of the analog signal. Another object of the present invention is to provide a system for converting an analog signal into a digital data stream that samples the spike outputs from a large number of A/D converters (e.g. 2,000) during a predetermined time interval (e.g. 100 picoseconds) to generate a digital stream indicative of the analog signal. Still another object of the present invention is to provide a system for converting an analog signal into a digital data stream that effectively suppresses SQNR. Another object of the present invention is to provide a system for converting an analog signal into a digital data stream that is simple to use, is relatively easy to manufacture, and is comparatively cost effective.